The present invention relates to a liquid crystal display for controlling the intensity of light according to the amplitude value of a voltage and, more particularly, to a liquid crystal light valve which is suitable for use in a projection type display.
Liquid crystal displays using an active matrix method, in which switching elements and liquid crystals are laminated for controlling a light, has been disclosed in U.S. Pat. No. 3,862,360 and in the IE80-81 technical report of The Institute of Electronics and Communication Engineers of Japan, 1980. The displays are of a direct viewing type in which an image controlled by the switching elements is directly seen. An MOS (metal oxide-semiconductor) transistor formed on a single crystal silicon substrate is used as a switching element.
When light is irradiated onto the MOS transistor, a photoelectric current is generated in a PN junction section in which a source and a drain are formed. When the photoelectric current is generated in a switching element section for controlling the liquid crystal, a voltage which is applied to the liquid crystal is changed so that the picture quality deteriorates. When the photoelectric current flows into the switching element or a drive circUit section for controlling the switching element, a phenomenon called "latch-up" is caused. A heavy current flows to the power supply, with the result that the circuit operation is disturbed and the chip is destroyed.
FIG. 20 is a schematic diagram of a CMOSLSI for explaining this latch-up phenomenon. A PMOS is formed on a surface of an n-type substrate and an MOS is formed in a p-well region. The substrate supplies a power to VDD (for example +5 V) through an n+ diffusion layer and the p-well supplies a power to VSS (for example, GND) through a p+ diffusion layer. An inverter circuit is constructed in a manner such that the sources of the PMOS and NMOS transistors are connected to VDD and VSS, the gates are combined and connected to an input terminal Vin, and the drains are combined and connected to an output terminal Vout, respectively
In the CMOSESI, parasitic bipolar transistors Tr1 and Tr2 and resistors R1 to R4 are used. The transistor Tr1 is an npn transistor in which the source of the NMOS is used as an emitter, the p-well is used as a base, and the substrate is used as a collector. The transistor Tr2 is a pnp transistor in which the source of the PHOS is used as a emitter, the substrate is used as an base, and the p-well is used as a collector. Reference characters R1 and R2 denote resistors formed by the p-well, and R3 and R4 denote resistors formed by the volume resistivity of the substrate.
Each of the parasitic bipolar transistors Tr1 and Tr2 has a thyristor structure as shown in the diagram. When a voltage between the terminals is increased by a trigger current Ip flowing into the parasitic resistor R1 or R4, the parasitic npn or pnp bipolar transistor is turned on. The "on" current flows in the parasitic resistor R1 or R4 and then rapidly increases. A heavy current flows between VDD and VSS, thereby causing a latch-up. Due to the latch-up phenomenon, the voltage in the circuit is decreased, thereby disturbing the circuit operation, and the interconnection layer or silicon substrate is melted, thereby destroying the chip.
The trigger current causing the latch-up occurs due to a light irradiation to the periphery of the MOS transistor in addition to power source noises and the like. Electrons or holes generated in the substrate by the light irradiation move to a PN junction between the substrate of a high electric field and the p-well and form the photoelectric current Ip. The photoelectric current Ip flows between the n+ diffusion region of the substrate and the p+ diffusion region of the p-well to form the trigger current in the thyristor structure.
In the technical report of The Institute of Electronics and Communication Engineers of Japan, (1980), it is described that a source region of an MOS transistor is disposed at a position as far as possible from a light incident region in a switching region of a semiconductor substrate and a stopper diffusion region for recouping carriers generated is provided in order to reduce the photoelectric current which is generated in the MOS transistor to prevent the latch-up.
Although an improvement which becomes less active was a big proposition for a display apparatus using the liquid crystal panel at the beginning, a larger size also has been required in recent years.
The liquid crystal panel consists of liquid crystal elements, each of which is independent for every pixel. The liquid crystal element itself doesn't emit light, but functions as a light valve which modulates the transmission of light and the resulting displays.
Recently, attention has been given to an apparatus in which characteristics as a light valve of the liquid crystal panel are effectively used and the apparatus is built so as to be large using a projection type display method.
The projection type display apparatus can be installed in various ways in accordance with the environment, for example, the apparatus may be installed on the floor, hung from the ceiling, or the like. Further, as projection modes of a screen for display, there are: a projection display from the back side using a projection type screen, and a projection display from the front using a reflection type screen. In order to correspond to the above, a mirror image inversion of an image is consequently necessary.
In such a case, generally, the mirror image inversion is achieved by inverting the horizontal and vertical scanning directions of each liquid crystal panel.
The number of pixels of the liquid crystal panel for the light valve used in the conventional projection type liquid crystal display apparatus usually coincides with the number of pixels necessary for image data to be displayed.
For example, in case of a VGA (Video Graphic Array) specification as a standard for a standard video image signal of a personal computer, the number of pixels of display image data is equal to 307,200 pixels (=640 pixels in the horizontal direction.times.480 pixels in the vertical direction). In this case, the number of pixels of the liquid crystal panel coincides with the number of pixels of the display data, that is, the number of pixels in a horizontal scanning line is equal to 640 and the number of scanning lines is equal to 480.
FIG. 21 shows a conventional horizontal scanning circuit used for such a liquid crystal panel, comprising a shift register 31 and a clock signal control circuit 39 which operates synchronously with a clock signal CLK.
The shift register 31 consists of a plurality of units 32 and operates in response to clock signals which are inverted and supplied from the clock signal control circuit 39 synchronously with the clock signal CLK to sequentially generate pulses to a plurality of data lines. The pulse drives the pixels of a horizontal scanning line H of the liquid crystal panel, thereby performing a scan.
The scanning direction of the shift register 31 is determined by a scanning direction control signal L/R in this instance. In both of the cases, the scan is started by a start pulse signal STA.
When it is assumed that the number of pixels in a scanning line H is equal to n (for instance, n=640), reference characters can be sequentially designated to the pixels in the scanning line H from the left, PH1, PH2, PH3, . . . , PHn-2, PHn-1, PHn in correspondence to a scan from left to right (L.fwdarw.R). On the other hand, reference characters can be sequentially designated from the right, PH(n), PH(n-1), PH(n-2), . . . , PH(3), PH(2), PM(1) in correspondence to a right to left scan (L.rarw.R).
Since the units 32 of the shift register 31 drive the scanning lines on the output side in the scanning direction, the units 32 of the number which is larger than the number of scanning lines by one are necessary for a bidirectional scan.
The number of units 32 of the shift register 31 is equal to n+1 (=641) in correspondence to the number of scanning lines n. As shown in the diagram, reference numerals are sequentially designated as 1, 2, 3, . . . , n-1, n, n+1 in correspondence to the left to right scan (L.fwdarw.R). Similarly, reference numerals are sequentially designated as (n+1), (n), (n-1), . . . , (3), (2), (1) in correspondence to the right to left scan (L.rarw.R).
That is, the number of units 32 of the shift register 31 is equal to 641 in correspondence to the 640 scanning lines in this case.
FIG. 22 is a timing chart showing the operation of the horizontal scanning circuit. The upper half shows a case where the scanning direction control signal L/R is set to the high level ("H") and the scanning direction is from left to right, and the lower half shows a case where L/R is set to the low level ("L") and the scanning direction is from right to left.
The shift register 31 sequentially shifts the pulses from a data line PH1 to a data line PHn and from a data line PH(n) to a data line PH(1) at both of the timings of a leading edge and a trailing edge of the clock signal CLK. It is understood that the shifting direction of the shift pulses is set from right to left or from left to right in accordance with the scanning direction control signal L/R.
A noticeable point here is that the positional relationship between the shift pulse and the clock signal is changed to the same data line in accordance with the scanning direction.
When it is assumed that the number of data in the horizontal scanning direction is equal to an even number (640) as in the case of the VGA specification, in case of the scan from left to right, the first scanning line number in the scanning direction is first which is an odd number and the last data line is 640th which is an even number.
On the contrary, in case of the scan from right to left, the first line corresponds to the 640th line in case of the left to right scan, so that it is an even-number line. On the other hand, the last (640th) line corresponds to the first line in the case of the left to the right scan, which is an odd number.
That is, the same data line becomes an odd number or an even number in accordance with the scanning direction in this case.
When it is assumed that the shift register executes a writing operation to a data line at both the leading and trailing edges of a clock signal, namely, the odd number is written to the data line at the trailing edge of the clock signal and the even number is written at the leading edge, the phase of the clock signal necessary to operate the unit in the shift register, which scans the odd-number data line and that of the unit which scans the even-number data line are different, in other words, they are inverted with respect to each other.
When the scanning direction is from left to right, the trailing edge of the clock signal has to appear first after the start pulse signal STA rises. When the scanning direction is from right to left, the leading edge of the clock signal has to appear first after the start pulse signal STA rises.
For this purpose, as shown in FIG. 22, it is consequently necessary to invert the phase of the clock signal HCK in accordance with the upper example of the left to right scanning direction and the lower example of the right to left scanning direction.
That is, if an operation is executed while the phase of the clock signal CLK is kept the same, as in the upper example and in the lower example of FIG. 22, a scan of the data line PH1 is started at a time point t.sub.0 when the clock signal CLK is trailed for the first time since a time point t.sub.H when the start pulse signal STA is generated in the upper example. On the contrary, the clock signal CLK rises at a time point t.sub.1, not the time point t.sub.0 in the lower example. The scanning start time point for the data line Hn consequently becomes t.sub.1, so that the operation is delayed by one clock period.
In the conventional example of the horizontal scanning circuit shown in FIG. 21, therefore, there is provided the clock signal control circuit 39 by which the phase of the clock signal CLK inputted from the outside is shifted in accordance with the scanning direction control signal L/R. The signal is supplied to the shift register 31, thereby obtaining the phase inversion of the clock signal CLK in accordance with the scanning direction as shown in FIG. 22.
Although only the horizontal scanning circuit has been described above, the vertical scanning circuit is substantially the same.
A conventional example of the shift register which can execute the above mentioned bidirectional scan and shifts at both timings of the leading and trailing edges of the clock signal is disclosed in, for example, Japanese Patent Application Laid-open HEI 2-137886.
The above-mentioned conventional liquid crystal display using the MOS transistor is of the direct viewing type, and approximately tens of thousands of lux is sufficient for light-fastness necessary for the display panel. In the projection type display, however, since a control image is enlarged and projected onto a screen, the light irradiated to the liquid crystal light valve is millions of lux. The conventional shading structure is consequently insufficient and a structure wherein the semiconductor substrate is completely covered against the incident light is necessary. Further, it is necessary to enhance the light-fastness in not only the switching area for controlling the image, but also for a drive circuit section disposed around the switching area.
In the above-mentioned liquid crystal panel, simplification of the peripheral circuits and the characteristics of change in association with the switching of the scanning directions are not sufficiently considered and there are problems of improvement of performance and cost reduction.
That is, it is necessary to invert the phase of the clock signal in accordance with the scanning direction, so that the clock signal control circuit is required in the conventional technique.
The clock signal control circuit doesn't change the phase of the inputted clock signal and outputs as it is in one scanning direction. The clock signal control circuit is switched to shift the phase of the inputted clock signal by .PI./2 in the other scanning direction. When a display is considered having a clock signal processing system, a symmetry of signal process paths is lost according to the scanning direction and a symmetry of layout in the peripheral circuits of the liquid crystal panel is also lost, so that the maximum operation speed can be changed according to the scanning direction.
For example, in case of a drive method for performing a writing operation to a data line on both of the leading and trailing edges of a clock signal, since it is necessary to hold a duty ratio of the clock signal to 50%, when the operation characteristics are different according to the scanning directions, a distortion in the clock signal waveform and the like is caused and is a big factor in the performance deterioration.
The frequency of the clock signal ranges from approximately 28 MHz in case of the VGA specification of (640 pixels.times.480 pixels) to approximately 130 MHz in case of a specification of (1280 pixels.times.1024 pixels) and a higher precision video signal standard, which is generally used for an engineering work station and the like. The peripheral circuits have to stably operate even at high frequencies, so that the peripheral drive circuits built in the panel are desirably as simple as possible.
As mentioned above, the conventional technique has problems related to performance and costs.